Package: inet.protocolelement.common
InterpacketGapInserter
simple module(no description)
Inheritance diagram
The following diagram shows inheritance relationships for this type. Unresolved types are missing from the diagram.
Used in compound modules
Name | Type | Description |
---|---|---|
EthernetPhyLayer | compound module | (no description) |
EthernetPreemptingPhyLayer | compound module | (no description) |
Extends
Name | Type | Description |
---|---|---|
PacketProcessorBase | simple module |
This is a base module for various packet processing modules which maintains a few statistics. |
Parameters
Name | Type | Default value | Description |
---|---|---|---|
displayStringTextFormat | string | "delayed %p pk (%l)\nifg: %g" |
determines the text that is written on top of the submodule |
clockModule | string | "" |
relative path of a module that implements IClock; optional |
initialChannelBusy | bool | false |
assume that channel was busy before the simulation started |
duration | double |
Properties
Name | Value | Description |
---|---|---|
display | i=block/timer | |
class | InterpacketGapInserter |
Gates
Name | Direction | Size | Description |
---|---|---|---|
in | input | ||
out | output |
Signals
Name | Type | Unit |
---|---|---|
interpacketGapEnded | double | |
interpacketGapStarted | double |
Statistics
Name | Title | Source | Record | Unit | Interpolation Mode |
---|---|---|---|---|---|
interpacketGap | interpacket gap state | count(interpacketGapStarted) - count(interpacketGapEnded) | vector | sample-hold |
Scheduled messages (observed)
msg | kind | ctrl | tags | msgname | context |
---|---|---|---|---|---|
ClockEvent | 0 | IfgTimer |
Direct method calls (observed)
call to | function | info |
---|---|---|
PcapRecorder | inet::PcapRecorder::receiveSignal | packetSentToLower |
Ieee8021qCreditBasedShaper | inet::queueing::CreditBasedGate::receiveSignal | interpacketGapEnded |
EthernetPhyHeaderInserter | inet::physicallayer::EthernetPhyHeaderInserter::handleCanPushPacketChanged | handleCanPushPacketChanged |
PacketEmitter | inet::PacketEmitter::pushPacket | pushPacket |
PacketEmitter | inet::PacketEmitter::pushPacketEnd | pushPacketEnd |
PacketEmitter | inet::PacketEmitter::pushPacketProgress | pushPacketProgress |
PacketTransmitter | inet::PacketTransmitter::pushPacket | pushPacket |
PacketMultiplexer | inet::queueing::PacketMultiplexer::handleCanPushPacketChanged | handleCanPushPacketChanged |
Called methods (observed)
function | info | call from |
---|---|---|
inet::InterpacketGapInserter::handleCanPushPacketChanged | handleCanPushPacketChanged | PacketEmitter, PacketTransmitter |
inet::InterpacketGapInserter::pushPacket | pushPacket | EthernetPhyHeaderInserter |
inet::InterpacketGapInserter::pushPacketEnd | pushPacketEnd | PacketMultiplexer |
inet::InterpacketGapInserter::pushPacketProgress | pushPacketProgress | PacketMultiplexer |
Pushed in messages (observed)
Push out messages (observed)
Source code
simple InterpacketGapInserter extends PacketProcessorBase { parameters: string clockModule = default(""); // relative path of a module that implements IClock; optional bool initialChannelBusy = default(false); // assume that channel was busy before the simulation started volatile double duration @unit(s); displayStringTextFormat = default("delayed %p pk (%l)\nifg: %g"); @display("i=block/timer"); @class(InterpacketGapInserter); @signal[interpacketGapStarted](type=double); @signal[interpacketGapEnded](type=double); @statistic[interpacketGap](title="interpacket gap state"; type=int; source=count(interpacketGapStarted) - count(interpacketGapEnded); record=vector; interpolationmode=sample-hold); gates: input in; output out; }File: src/inet/protocolelement/common/InterpacketGapInserter.ned