InterpacketGapInserter

simple module

(no description)

Inheritance diagram

The following diagram shows inheritance relationships for this type. Unresolved types are missing from the diagram.

Used in compound modules

Name	Type	Description
EthernetPhyLayer	compound module	(no description)
EthernetPreemptingPhyLayer	compound module	(no description)

Extends

Name	Type	Description
PacketProcessorBase	simple module	This is a base module for various packet processing modules which maintains a few statistics.

Parameters

Name	Type	Default value	Description
displayStringTextFormat	string	"delayed %p pk (%l)\nifg: %g"	determines the text that is written on top of the submodule
clockModule	string	""	relative path of a module that implements IClock; optional
initialChannelBusy	bool	false	assume that channel was busy before the simulation started
duration	double

Properties

Name	Value	Description
display	i=block/timer
class	InterpacketGapInserter

Gates

Name	Direction	Size	Description
in	input
out	output

Signals

Name	Type	Unit
interpacketGapEnded	double
interpacketGapStarted	double

Scheduled messages (observed)

msg	kind	ctrl	tags	msgname	context
ClockEvent	0			IfgTimer

Direct method calls (observed)

call to	function	info
PcapRecorder	inet::PcapRecorder::receiveSignal	packetSentToLower
EthernetPhyHeaderInserter	inet::physicallayer::EthernetPhyHeaderInserter::handleCanPushPacketChanged	handleCanPushPacketChanged
PacketEmitter	inet::PacketEmitter::pushPacket	pushPacket
PacketTransmitter	inet::PacketTransmitter::pushPacket	pushPacket

Called methods (observed)

function	info	call from
inet::InterpacketGapInserter::handleCanPushPacketChanged	handleCanPushPacketChanged	PacketEmitter, PacketTransmitter
inet::InterpacketGapInserter::pushPacket	pushPacket	EthernetPhyHeaderInserter

Pushed in messages (observed)

gate	msg	kind	ctrl	srcModule	tags
in	Packet	0		EthernetPhyHeaderInserter	DirectionTag, InterfaceReq, MacAddressReq, PacketProtocolTag, DispatchProtocolInd?, DropEligibleInd?, DropEligibleReq?, EcnInd?, Ieee802SapReq?, InterfaceInd?, MulticastReq?, NetworkProtocolInd?, PcpInd?, PcpReq?, SocketReq?, TransportProtocolInd?, UserPriorityInd?, UserPriorityReq?, VlanInd?

Push out messages (observed)

gate	msg	kind	ctrl	destModule	tags
out	Packet	0		PacketEmitter	DirectionTag, InterfaceReq, MacAddressReq, PacketProtocolTag, DispatchProtocolInd?, DropEligibleInd?, DropEligibleReq?, EcnInd?, Ieee802SapReq?, InterfaceInd?, MulticastReq?, NetworkProtocolInd?, PcpInd?, PcpReq?, SocketReq?, TransportProtocolInd?, UserPriorityInd?, UserPriorityReq?, VlanInd?
out	Packet	0		PacketTransmitter	DirectionTag, InterfaceReq, MacAddressReq, PacketProtocolTag, DispatchProtocolInd?, MulticastReq?, NetworkProtocolInd?, TransportProtocolInd?

Source code

simple InterpacketGapInserter extends PacketProcessorBase
{
    parameters:
        string clockModule = default(""); // relative path of a module that implements IClock; optional
        bool initialChannelBusy = default(false); // assume that channel was busy before the simulation started
        volatile double duration @unit(s);
        displayStringTextFormat = default("delayed %p pk (%l)\nifg: %g");
        @display("i=block/timer");
        @class(InterpacketGapInserter);
        @signal[interpacketGapStarted](type=double);
        @signal[interpacketGapEnded](type=double);
    gates:
        input in;
        output out;
}

File: src/inet/protocolelement/common/InterpacketGapInserter.ned